1. Field of the Invention
The present invention relates to a compound semiconductor device used, for example, for monolithic microwave integrated circuits (MMIC) and to a method for fabricating the device.
2. Description of the Related Art
In recent years, a high electron mobility transistor (HEMT) has come into use for high-speed digital circuits, such as the signal processing circuits of optical communications systems, from the viewpoint of a high-speed characteristic. Also from the viewpoint of a low-noise characteristic, the HEMT is expected to be applied to low-noise amplifiers used in a microwave or millimeter wave band. InP and GaAs are used mainly as materials for the HEMT, thus providing the HEMT in the form of a heterojunction field-effect transistor.
In a previous HEMT, an n-type impurity was uniformly doped into an electron supply layer. In recent years however, a technique for planar-doping silicon (Si) or other materials into the electron supply layer has been frequently used in order to improve the high-speed characteristic. Such a technique is disclosed in, for example, Patent Document 1 (Japanese Patent Application Laid-Open No. Hei 9-139494). FIG. 9 is a cross-sectional view illustrating the structure of a conventional compound semiconductor device.
In a conventional compound semiconductor device, an intrinsic InAlAs layer 102 is selectively formed on an InP substrate 101, and then an intrinsic InGaAs layer 103, an intrinsic InAlAs layer 104, a Si planar-doped layer 106 and an intrinsic InAlAs layer 107 are successively stacked on the intrinsic InAlAs layer 102. Then, n-type InGaAs layers 108 are formed in two places on the intrinsic InAlAs layer 107, and then a source electrode 109S and a drain electrode 109D are formed on the n-type InGaAs layers 108, respectively. In addition, a gate electrode 110 is formed in an area between the source electrode 109S and the drain electrode 109D on the intrinsic InAlAs layer 107.
In this structure, the Si planar-doped layer 106 is provided in a location where an n-type InAlAs layer used to be provided as an electron supply layer. According to such a structure, it is possible to improve the transconductance gm and keep the carrier concentration Ns sufficiently high, compared with the previous compound semiconductor device, thereby improving the high-speed characteristic. However, the high-speed characteristic available with this structure is not adequate, either.
Generally speaking, it is possible to improve the transconductance gm further by increasing the concentration of an impurity in the Si planar-doped layer 106. However, increasing the concentration results in an increase in the amount of impurity diffusing into the channel, causing the impurity to serve as a source of electron scattering. As a result, the low-noise characteristic, one of the HEMT's features, will degrade.
In the conventional art, however, importance is attached to the high-speed characteristic at the sacrifice of the low-noise characteristic. For example, in the conventional compound semiconductor device shown in FIG. 9, the distance between the intrinsic InGaAs layer 103 functioning as a channel layer and the Si planar-doped layer 106 is approximately 2 to 3 nm. Thus the impurity sufficiently diffuses into the channel layer.
On the other hand, a compound semiconductor device using both a layer doped with an n-type impurity as an electron supply layer and a planar-doped layer is disclosed in Patent Document 2 (Japanese Patent Application Laid-Open No. Hei 11-214676). FIG. 10 is a cross-sectional view illustrating the structure of another conventional compound semiconductor device.
In this compound semiconductor device, an intrinsic InAlAs layer 112 is selectively formed on an InP substrate 111, and then an intrinsic InGaAs layer 113, an intrinsic InAlAs layer 114, an n-type InAlAs layer 115, a Si planar-doped layer 116, and an n-type InAlAs layer 117 are successively stacked on the intrinsic InAlAs layer 112. Then, n-type InGaAs layers 118 are formed in two places on the n-type InAlAs layer 117, and then a source electrode 119S and a drain electrode 119D are formed on the InGaAs layers 118, respectively. In addition, a gate electrode 120 is formed in an area between the source electrode 119S and the drain electrode 119D on the n-type InAlAs layer 117.
Also in this structure, however, the low-noise characteristic is sacrificed. Another problem is that the n-type InAlAs layer 117 must be thickened in order to ensure an adequate gate withstand voltage. It is thus difficult to satisfy requirements for both the gate withstand voltage and the high-speed characteristic.
This problem has not yet been solved either by the technique disclosed in Patent Document 3 (Japanese Patent Application Laid-Open No. Hei 8-55979 (Japanese Patent No. 2661555)). More particularly, although Patent Document 3 discloses the technique for forming a Si planar-doped layer on an intrinsic InAlAs layer and then an n-type InAlAs layer on the Si planar-doped layer, it is difficult to satisfy the respective characteristics.